Capacitors for semiconductor devices may be classified based upon the type of the capacitor electrode, such as metal-insulator-metal (MIM) capacitors and polysilicon-insulator-polysilicon (PIP) capacitors. PIP capacitors may exhibit problems of high specific resistance and parasitic capacitance occurred due to a depletion phenomenon. For this reason, MIM capacitors may be generally used in which copper wiring with low specific resistance is employed.
As illustrated in example FIG. 1, a semiconductor device having a conventional MIM capacitor may include first insulating film 12 formed on and/or over semiconductor substrate 10. Lower electrode 14 may be formed on and/or over first insulating film 12 and second insulating film 16 may be formed on and/or over lower electrode 14. Upper electrode 18 may be formed on and/or over second insulating film 16 and third insulating film 20 may be formed on and/or over upper electrode 18. Interlayer dielectric film 22 may be formed over the entire surface of semiconductor substrate 10 including first insulating film 12, lower electrode 14, second insulating film 16, over upper electrode 18, third insulating film 20.
A method for manufacturing the MIM capacitor having such a structure may include sequentially forming first insulating film 12, lower metal layer 14a, second insulating material 16a, upper metal layer 18a and third insulating material 20a on and/or over semiconductor substrate 10 in accordance with a deposition technique such as plasma enhanced chemical vapor deposition (PECVD) or sputtering.
First insulating film 12, second insulating material 16a and third insulating material may be composed of silicon nitride (SiN). Lower metal layer 14a may be composed of at least one of titanium (Ti) and titanium nitride (TiN). Upper metal layer 18a may be composed of titanium nitride (TiN).
As illustrated in example FIG. 2A, first photoresist pattern 24 may then be formed on and/or over third insulating material 20a by a photolithographic process using a first mask. First photoresist pattern 24 may be formed in a region where upper electrode 18 is formed.
As illustrated in example FIG. 2B, third insulating material 20a and upper metal layer 18a may be patterned by etching through first photoresist pattern 24, thereby forming third insulating film 20 and upper electrode 18. First photoresist pattern 24 may then be removed by ashing.
As illustrated in example FIG. 2C, second photoresist pattern 26 may be formed on and/or over second insulating material 16a by a photolithographic process using a second mask such that it covers third insulating film 20 and upper electrode 18. Second photoresist pattern 26 may be formed in a region where lower electrode 14 is formed.
As illustrated in example FIG. 2D, second insulating material 16a and lower metal layer 14a may then be patterned by etching through second photoresist pattern 26, thereby forming second insulating film 16 and lower electrode 14.
As illustrated in example FIG. 2E, second photoresist pattern 26 may then be removed by ashing.
As illustrated in example FIG. 2F, interlayer dielectric film 22 may then be formed on and/or over the entire surface of the semiconductor substrate 10 including the resulting structure.
MIM capacitors may be formed through a two-step masking process, requiring the use of two masks, in order to form upper electrode 18 and lower electrode 14. This is because when upper electrode 18 and lower electrode 14 are etched using a single mask, there occurs short-circuiting between the two electrodes. That is, due to the resputtering involved in the formation of lower electrode 14, the conductive etch by-products are formed on the side walls of upper electrode 18, thus causing short-circuiting between the two electrodes.
Accordingly, in MIM capacitor techniques, two masking processes may be required to form upper electrode 18 and lower electrode 14. Thus, since MIM capacitors may be formed using the two-step masking process, they have a disadvantage of high manufacturing costs caused by expensive masks. For this reason, there is a need for methods for manufacturing MIM capacitors that are capable of reducing manufacture costs via simplification of mask processes.